Target-Voltage LDMOS Device Design Intuition Lab v0.2

What This Lab Teaches

The target-voltage LDMOS topic is not simply “create a higher-voltage device.” It is about opening a usable design window while balancing breakdown margin, operating margin, on-resistance, capacitance, and reliability.

One-line intuition

The target-voltage design problem is a bridge problem: use controlled device engineering to reach the desired operating window without forcing an overly conservative, high-capacitance, or high-resistance solution.

1. Device physics

LDMOS breakdown is shaped by electric field distribution in the drift region and field-plate geometry.

Breakdown is not one number; it is the result of field shaping.

2. Design tradeoff

Higher BV often increases drift length, resistance, capacitance, or reliability constraints.

A “safer” device can cost efficiency and speed.

3. Design enablement

The design value is scalable geometry support, not just a one-off fixed point.

Design freedom is the key learning point.

Master mental model

Need target voltage

→

Voltage gap

→

Field-plate scaling

→

BV / on-resistance / C tradeoff

→

Silicon + model support

→

Design validation

Use-case map

Use case	Main risk	What matters most
Efficient power stage	High on-resistance penalty	Low resistance at sufficient BV
Fast switching / level shift	Large Coss or parasitic capacitance	Capacitance and dynamic behavior
Robust operating margin	breakdown too close to operating stress	breakdown margin, operating margin, and reliability behavior
Conservative design path	Aggressive option may carry higher validation risk	Conservative backup design choice

1. First-Principle Physics

LDMOS design is controlled by lateral electric field. The device must spread voltage safely while still conducting current efficiently.

Breakdown voltage

BV ≈ function(E_peak, drift length, doping, field plate, junction curvature)

Breakdown occurs when the peak electric field becomes high enough to trigger avalanche multiplication.

BV is often limited by the worst local field point, not the average field.

On-resistance

R_on ≈ R_channel + R_drift + R_contact + R_metal

For LDMOS, the drift region contribution often grows when the device is engineered for higher voltage.

Higher BV usually costs on-resistance unless field engineering is improved.

Core device knobs

Knob	Physical role	Tradeoff
Drift length	Spreads voltage over longer distance	Improves BV but increases on-resistance and area
Drift doping	Controls depletion and conduction	Higher doping lowers on-resistance but reduces breakdown margin
Field-shaping geometry	Shapes electric field near drain/drift region	Can improve field distribution but changes capacitance
Device family split	Different geometry/model regimes	Can create voltage coverage gaps
Operating voltage definition	Reliability-safe use condition	Not equal to BV; includes HCI and margin

Visual: field shaping

Field plate geometry can redistribute field and open intermediate BV design space.

Key first-principle insight

To reach ~target voltage, the device does not simply need “more breakdown margin.” It needs the right BV with acceptable resistance, capacitance, and operating reliability.

A device that survives voltage but loses too much efficiency may not solve the designer’s real problem.

2. Why the Gap Exists

The voltage gap is created by how device families are separated. One family covers lower operating voltage; another covers higher operating voltage. The boundary is driven by physical geometry and model validity.

Baseline device-space idea

Lower-voltage family: optimized for lower operating range and better efficiency.
Medium-voltage family: optimized for higher field handling and reliability.
Between them, there can be a design gap where neither family is ideal.

The target-voltage requirement often lives in this intermediate optimization region.

Why not just use higher-voltage device?

May have larger drift region or geometry.
May increase on-resistance.
May increase Coss / parasitic capacitance.
May reduce speed or efficiency.

Over-voltage choice can be safe but inefficient.

Field-plate / DE-like scaling intuition

A key physical idea is that device families are often separated by field-shaping geometry. Geometry controls how the device spreads electric field between source and drain.

Region	Physical picture	Design consequence
Too short / low-voltage-like	Field may crowd too strongly near drain/drift edge	breakdown margin limited
Intermediate	Field is shaped enough for mid-voltage operation	Target region for voltage-window optimization
Too long / high-voltage-like	Safer field distribution but larger device penalty	More on-resistance / capacitance / area

The gap is not random. It comes from discrete geometry/model regimes and reliability limits.

Design-context upgrade: why scalability matters

A designer may initially worry that only one fixed geometry is available.
The stronger design approach is scalable geometry support across a validated range.
The value is that a designer can tune the device to the specific system need.

Design value = scalable optimization space, not one fixed geometry.

Gap memory model

Lower-voltage efficient

→

Higher-voltage robust

→

Gap between families

→

Scale robust family downward

→

Bridge target window

3. Tradeoff Mechanisms

There is no perfect device. The right choice depends on how much breakdown margin, on-resistance, Coss, speed, reliability, and schedule risk the product can tolerate.

Core tradeoff table

Approach	Benefit	Cost / risk	Best explanation
Scale lower-voltage device upward	Can preserve lower-voltage device efficiency for some range	breakdown / reliability / HCI margin may become limiting	Good if margin is enough; risky if pushed too hard
Scale medium-voltage device downward	Can bridge mid-range with more robust field architecture	May have Vop / model boundary / capacitance considerations	Promising path if silicon + model support is confirmed
Use conservative higher-voltage device	Strong margin and simpler risk story	Efficiency hit from higher on-resistance / capacitance / area	Good fallback, not always optimal
Use aggressive scaled geometry	Optimizes efficiency for the target window	Needs careful model and reliability validation	Best for performance path with fallback plan

on-resistance intuition

R_drift ∝ L_drift / (q · μ · N_drift · Area)

More drift length or lower drift doping improves voltage handling but increases resistance.

breakdown margin often costs conduction efficiency.

Coss intuition

C_oss ≈ C_drain-body + C_drain-gate + C_drain-isolation

More voltage-tolerant structures can add parasitic capacitance. In fast circuits, this can slow switching or increase dynamic loss.

A device can look good in DC but hurt AC/system performance.

Reliability constraints

BV is not the same as allowed operating voltage.
Operating voltage also depends on HCI, BVon/BVoff, and safe margin.
Device scaling must stay inside validated reliability space.

Do not equate “breakdown is above X” with “safe to operate at X.”

Aggressive + conservative design strategy

Aggressive path: use the newly enabled target-window optimization region.
Conservative path: use a more established LDMOS option with an efficiency penalty.
This lets product move forward while reducing risk.

Parallel design paths are a rational risk-management strategy.

Tradeoff memory model

breakdown margin

↔

on-resistance

↔

Coss

↔

Reliability

↔

Schedule risk

4. Modeling & Limits

A strong device story needs both silicon evidence and model support. But simulation has limits, especially near breakdown, avalanche, and stress behavior.

Minimum useful model view

Ids = f(Vgs, Vds, Vbs, geometry) Coss = f(Vds, geometry) breakdown / reliability = checked against validated range

The A model should support geometry scaling, DC behavior, capacitance, and operating-condition checks over the validated range.

Geometry support without model support is not enough.

Measurement + model correlation

Measurement data validates physical trends.
Model checks confirm that the compact model can represent the design range.
The usable design range should match the validated geometry range.

The strongest engineering story is: physical scaling is smooth and model behavior remains credible.

Model limitation map

Phenomenon	May be modeled well?	Risk
Normal DC I-V	Usually yes inside validated range	Depends on geometry coverage
Capacitance vs voltage	Usually modeled if characterized	Critical for Coss / switching
HCI / reliability rules	Often through operating limits, not pure SPICE	Needs rule/limit interpretation
Parasitic bipolar triggering	May show some behavior	Full breakdown point may not be captured
Avalanche breakdown / UIS	Often limited in compact models	Needs silicon characterization

Engineering caution

Simulation can guide device choice, but avalanche, UIS, and extreme transient robustness need measurement-backed understanding. Do not make the compact model carry the full safety argument.

Checklist before calling a device “usable”

Is the geometry range explicitly supported?
Is the model valid over that geometry range?
Are capacitance and Coss trends available?
Are operating limits clear?
Is breakdown margin sufficient relative to system stress?
Is there a conservative fallback path?
Is measurement evidence available for the intended use range?

5. Visual Sandbox

Use this simple interactive model to feel the breakdown/on-resistance/capacitance tradeoff when scaling toward a target operating-voltage window.

Interactive inputs

Target operating-voltage window: 60%

Robust-family scaling aggressiveness: 65%

Required robustness margin: 20%

Coss / speed sensitivity: 50%

Tradeoff plot

Blue: approximate usable BV region. Orange: relative on-resistance penalty. Purple: relative Coss penalty.

Design score

breakdown margin score

—

Efficiency score

—

6. Decision Engine

This is the “what should I do?” layer. It converts device physics into design and support decisions.

Device selection matrix

Design situation	Suggested direction	Why
Need target voltage and high efficiency	Evaluate a scalable medium-voltage design range	Targets the design window without excessive conservative penalty
Need maximum robustness / schedule certainty	Use conservative higher-voltage fallback	Reduces risk at cost of efficiency
Fast switching node sensitive to Coss	Compare capacitance, not just on-resistance/BV	Coss can dominate dynamic behavior
Unclear stress waveform	Request operating conditions and transient profile	breakdown voltage alone is insufficient
UIS / avalanche exposure	Do not rely only on compact model	Needs measured robustness data

Rule-of-thumb engine

IF target voltage is higher AND efficiency matters: evaluate a scalable medium-voltage option IF robustness is uncertain: keep conservative fallback IF switching speed matters: compare Coss and dynamic loss IF avalanche / UIS is relevant: require silicon characterization IF Design validation timing matters: separate critical vs nice-to-have items

Design review checklist

What is the maximum steady-state Vds?
What is the transient overshoot?
Is the stress repetitive or rare?
Is the limiting factor on-resistance, Coss, BV, or reliability?
Does the chosen geometry fall inside the validated model range?
Is model support available for that range?
Is there a conservative fallback device?

Final engineering insight

The design decision is not “which device has the highest breakdown voltage?” It is “which device gives enough breakdown margin with the least penalty in on-resistance, capacitance, area, reliability risk, and schedule risk?”

Decision memory model

Target voltage

→

Stress margin

→

Efficiency penalty

→

Coss penalty

→

Model validity

→

Device choice

7. Meeting / Teaching Script

Use this tab to explain the topic clearly to BU, DE managers, customers, or future learners.

30-second explanation

“The target-voltage LDMOS topic is about bridging a practical device-design gap. Lower-voltage designs are efficient but may not provide enough margin, while higher-voltage designs may be more conservative but can cost on-resistance, capacitance, and area. The engineering direction is to create a scalable design window rather than forcing a single fixed point.”

Teaching-Safe Phrases

“This extends the usable design space in an intermediate voltage window.”

“Measurement and model alignment support this scaling direction.”

“The value is scalable geometry support, not just a one-off device.”

“The final choice depends on on-resistance, Coss, operating margin, and stress conditions.”

Avoid phrases

“This device solves all target-voltage needs.”

“Breakdown voltage equals safe operating voltage.”

“The model captures all breakdown behavior.”

“You should use this exact geometry.”

Teaching flow

Step	Say this	Why
1	“Start with the need: target operating-voltage coverage.”	Anchor to designer problem.
2	“Explain why device-family boundaries exist.”	Show why a gap exists.
3	“Introduce field-plate / scaling control.”	Connect physics to layout parameterization.
4	“Show tradeoffs: BV, on-resistance, Coss, reliability.”	Avoid oversimplification.
5	“Close with scalable design freedom.”	Explain design value.