Interactive LDMOS Explorer

Turn the knobs and observe how current flows through a power MOS device. The top plot shows drain current; the bottom plot reveals where the voltage drops inside the device — between the channel and the drift region.

Channel vs drift

A lateral DMOS is not controlled only by the channel. At higher drain bias, the drift region can become the dominant bottleneck even after the channel is already on.

Internal handoff

The internal handoff variable is a compact way to visualize where the device “decides” how much voltage is dropped in the channel-side portion versus the drift-side portion.

Bias tells the story

Sweeping gate bias shows turn-on behavior. Sweeping drain bias shows when the device transitions toward drift-limited behavior. Together they tell a richer power-device story than a simple MOSFET demo.

Figure 1. LDMOS voltage-drop intuition

static explainer

This lab focuses on the internal redistribution story: as bias changes, the device can move from channel-dominated behavior toward drift-dominated behavior.

Figure 2. From knobs to behavior

concept chain

The most important educational step is the middle one: bias and parameters reshape the internal balance, which then determines both current and where voltage is being spent inside the device.

Figure 3. Channel-limited vs drift-limited

behavior comparison

Improving the channel helps most when the channel is the bottleneck. Once the drift region dominates, further channel improvement produces diminishing returns.

Figure 4. Reading the handoff curve

plot interpretation

The lower plot is not just another output. It is the main internal-intuition plot. A flattening trend is the visual clue that the drift side is taking over more of the voltage burden.

Knobs Bias + high-level physics

Primary controls

Keep the main bias knobs visible so it is easier to click Sweep & Plot and immediately focus on the displayed results.

Secondary model parameters channel + drift detail knobs

These parameters are useful when you want to fine-tune channel-side or drift-side behavior, but they can stay collapsed during routine interactive viewing.

Evaluate updates the readout at the current bias point. Sweep plots how behavior changes when you vary one knob.

What’s happening?
In a power MOS device, not all of the drain voltage drops across the channel. Part of it is taken by the drift region, which can become the limiting factor at high voltage. The bottom plot tracks an internal “handoff” point. When that curve flattens, the device is no longer channel-limited.

Readout

The top four values stay visible. Secondary quantities are tucked into a compact expandable block.

Vg = turn-on control Vd = drift stress probe G0 / Vp = drift-side openness

Scope Id Internal handoff

Sweep (vary one knob)

From

Points

Try this: fix Vg, sweep Vd, and compare the two plots — you’ll see when the drift region starts dominating the voltage drop.

Tip: start with the default values. Sweep Vg to see turn-on, then sweep Vd to see drift-limited behavior.

Explain Intuition first

Many MOSFET demos focus only on the channel. Power devices are different: a large part of the drain voltage can drop in the drift region. This page lets you “see inside” by tracking an internal handoff point.

What to look for

Top plot (Id): how much current flows for your bias point.
Bottom plot (handoff): where the voltage is dropping inside the device.
If the handoff curve flattens as you increase Vd, the drift region is taking over.

Two “knobs” families

Channel knobs (Vth0, kappa, n, lambda) change how easily the channel conducts.
Drift/JFET knobs (G0, Vp, Vscale, gmin) change how strongly the drift region limits current.

Explain + Math (optional)

The model splits the device into a MOS-like channel core and a drain-side drift/JFET region.
An internal handoff point is chosen so the same current flows through both pieces.

The “engine” is intentionally hidden so you can focus on behavior and intuition. If you want deeper details later, this page can be extended with a full surface-potential MOS core and richer charge/Cap models.

Suggested experiments

Fix Vg, sweep Vd: watch when drift limitation appears.
Fix Vd, sweep Vg: watch channel turn-on and how it changes Id.
Increase G0 and see the drift region “open up” (more current, less limitation).

How the simulator works

This lab uses a compact split-device viewpoint. A MOS-like channel core and a drain-side drift/JFET-like region must both carry the same current. The internal handoff variable helps reveal how the total drain bias is partitioned between those pieces.

Id is constrained by both channel-side conduction and drift-side conduction.
Vdi is an internal partition variable, not a directly measured terminal voltage.
When Vdi response softens or flattens under increasing Vd, the drift side is becoming the stronger limiter.

Channel knobs mostly move turn-on and low-bias behavior.
Drift knobs mostly move high-voltage current limitation and internal voltage sharing.
Temperature and body bias let you see how secondary effects can reshape the balance.

Figure 5. Parameter-to-meaning map

reading guide

Control	Main meaning	Typical visual effect
Vg	gate-drive strength / turn-on	raises Id strongly once channel turns on
Vd	applied drain-side stress	reveals drift-limited behavior and handoff flattening
Vb	body-bias influence on channel	shifts turn-on tendency and channel response
T	simple temperature dependence	changes current level and balance subtly
Vth0, kappa, n, lambda	channel-family knobs	mostly reshape turn-on and MOS-side current response
G0, Vp, Vscale, gmin	drift/JFET-family knobs	mostly reshape drift-side openness, softness, and limitation

Assumptions and scope

important note

This lab is intentionally simplified so the user can focus on internal voltage sharing and current limitation rather than on full compact-model complexity.

high-level channel and drift abstractions instead of a production-qualified model
internal handoff variable for intuition, not direct physical extraction
generic educational parameterization rather than process-specific calibration
public-facing intuition tool, not a tapeout-ready device simulator

How to read the two plots together

usage note

The top plot tells you how much current the device is willing to deliver. The bottom plot tells you why that current is changing by revealing where the internal voltage burden is shifting. Reading them together is the key educational move in this lab.

Why this lab is useful

LDMOS devices are often taught using only terminal I-V curves. This lab adds a second layer of intuition by exposing an internal balance variable, which makes power-device behavior easier to explain and remember.

Real-world interpretations

The same intuition can support discussions about Rdson tradeoffs, high-voltage device design, channel optimization limits, drift engineering, and why improving one region does not always improve the whole device equally.